1. Field of the Invention
This patent specification relates to a synchronous rectification switching regulator, and more particularly, to a synchronous rectification switching regulator capable of operating at high frequencies and with high efficiency at low load currents, and a control circuit and a control method for controlling the synchronous rectification switching regulator.
2. Discussion of Related Art
There are known a synchronous rectification system and a non-synchronous rectification system as rectification systems for a step-down DC-DC converter with an inductor. Such a step-down DC-DC converter operates in two modes: a continuous mode during high loads and a discontinuous mode during low loads. In the continuous mode, a current continuously flows through an inductor. In the discontinuous mode, there are times during which no current flows through the inductor. In the synchronous rectification system, a step-down DC-DC converter operates at high efficiency in the continuous mode. In the discontinuous mode, a reverse current is generated, i.e., a current flows backward from a load side to ground through a synchronous rectification transistor, which leads to an extreme efficiency drop. To prevent the reverse current, a step-down switching regulator 100 illustrated in FIG. 1 is used.
In FIG. 1, when a pulse width modulated (PWM) signal is low, a switching transistor SWa is turned on, and the output of an AND circuit 102 is low, thereby turning off a synchronous rectification transistor SWb. Consequently, electrical power is supplied from a power supply Vdd to an output terminal 103 through the switching transistor SWa and an inductor La.
When a PWM signal is high, the switching transistor SWa is turned off. The voltage at a node a lowers to a negative voltage due to the back electromotive force by the inductor La, and therefore the output of a comparator 101 is high. As a result, both inputs to the AND circuit 102 are high, and thus the output of the AND circuit 102 is high, thereby turning on the synchronous rectification transistor SWb. Consequently, electrical power is supplied from a ground power supply Vss to the output terminal 103 through the synchronous rectification transistor SWb and the inductor La.
Then, in the discontinuous mode, in which a low load current flows through a load connected to the output terminal 103, the current flowing in the direction from the ground power supply Vss to the output terminal 103 gradually decreases to zero while the PWM signal is high. Thereafter, a current flows in the reversed direction, i.e., from the output terminal 103 to the ground power supply Vss, causing the voltage at the node a to be reversed to positive and the output of the comparator 101 to be low. Therefore, the output of the AND circuit 102 is low, which turns off the synchronous rectification transistor SWb, thus preventing generation of the reverse current from the output terminal 103 to the ground power supply Vss.
With advances in semiconductor technology, transistors that can perform switching to high frequencies have been produced. In addition, reduction in size of components including capacitors and inductors are desired for portable devices, for example, a mobile telephone. However, inductors have a current rating and the current rating of a small inductor is not large. To maximize the capabilities of such a small inductor, it is desirable that the switching frequencies of the switching transistor SWa and the synchronous rectification transistor SWb be increased. In a step-down switching regulator, when a current continuously flows, i.e., under high loads, a current imax flowing through an inductor has the following relationship:imax=iout+Vout/(2×L)×Toff where iout represents the output current from an output terminal, Vout represents the output voltage from the output terminal, L represents the inductance of the inductor, and Toff represents a period of time during which a switching transistor is off. Thus, in maintaining the output voltage Vout, an on-duty cycle of the switching transistor is independent of the frequency of an oscillator circuit that is used in generating PWM signals.
In FIG. 1, when the PWM signal changes from low to high, the switching transistor SWa is immediately turned off, whereas the synchronous rectification transistor SWb remains off until the comparator 101 changes its output to high. When the switching transistor SWa is off, a current flows from the inductor La, and therefore a current flows from the ground power supply Vss to the output terminal 103. At this point, when the synchronous rectification transistor SWb is off, a current flows through the synchronous rectification transistor SWb via a parasitic diode thereof. Therefore, the efficiency drops under high loads as a current flows via the parasitic diode. As the frequency of the PWM signal increases, the period of off-time of the synchronous rectification transistor SWb affects the efficiency. To deal with this, it is desirable that the comparator 101 respond quickly by increasing a bias current in the comparator 101.
Under low loads, as in the case of high loads, the synchronous rectification transistor SWb remains off until the comparator 101 reacts and changes its output to high when the PWM signal changes from low to high. However, the output current iout is small during low loads. Thus, the drop of efficiency caused by the current flowing via the parasitic diode of the synchronous rectification transistor SWb is relatively small in comparison with that during high loads. When the synchronous rectification transistor SWb is turned on and the current flowing from the ground power supply Vss to the output terminal 103 is reduced to zero, a reverse current begins to flow backward from the output terminal 103 to the ground power supply Vss. To cut off this current, the synchronous rectification transistor SWb is turned off by using the comparator 101 and the AND circuit 102. In this case, when the comparator 101 responds slowly, a current flows backward from the output terminal 103 to the ground power supply Vss, resulting in a drop of efficiency. Therefore, it is desirable that the comparator 101 respond quickly to reduce a time delay in the comparator 101. Thus, increasing a bias current in the comparator 101 is desired.
However, when a bias current is increased in the comparator 101 during low loads, the current consumption of the step-down switching regulator 100 increases, resulting in decrease of efficiency. This occurs particularly in pulse frequency modulation (PFM) control that thins switching operations.